The Hyperstone RISC technology is based on a load-store architecture. It is register-oriented and built around a 32-bit wide register stack that holds 64 general purpose local registers and 26 global registers. Load and store instructions are pipelined to a depth of 2 stages at the memory bus.The DSP unit also operates on the register set of the architecture in parallel to the ALU and load/store unit. It executes a dedicated DSP instruction set. Like the other instructions, the DSP instructions are strictly following RISC-principles. During the latency cycles of DSP instructions the ALU and load/store unit can execute other instructions.
Thus, a much higher degree of flexibility is achieved compared to conventional DSP implementations. Additionally, up to three operations per clock cycle can be executed. Therefore, a peak performance of up to 300 MOPS at 100 MHz can be achieved.
| RISC / DSP Architecture
) | Block Diagram of Hyperstone E1-32X RISC/DSP |
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Load-Store Architecture utilized by ALU and DSP Instructions
The hyperstone RSC/DSP architecture has a set of totally 96 32-bit registers, of which 64 are local registers and the others are global registers.
The register stack is organized as a circular buffer and uses the concept of overlapping stack frames. Hyperstone RISC/DSP processors use variable length instructions with 16, 32, and 48 bit instructions. Very useful are the integrated timers, the interrupt handler and the comprehensive bus interface for glue-less connection of any kind of memory and periphery. An automatic power-down mechanism further reduces the already low power consumption which is one result of the compact design.
The register stack is organized as a circular buffer and uses the concept of overlapping stack frames. Hyperstone RISC/DSP processors use variable length instructions with 16, 32, and 48 bit instructions. Very useful are the integrated timers, the interrupt handler and the comprehensive bus interface for glue-less connection of any kind of memory and periphery. An automatic power-down mechanism further reduces the already low power consumption which is one result of the compact design.
On-chip DSP-features for demanding multimedia/telecom applications
The DSP unit of the Hyperstone RISC/DSP is strictly following RISC principles. Like the ALU, all DSP instructions are working on the register set of the architecture, thus making data transfer between ALU and DSP part transparent. The DSP unit gives support for 16-bit and 32-bit data types. In order to achieve highest data throughput the DSP unit provides dedicated result registers and a 32-bit hardware accumulator as well as a 64-bit hardware accumulator.
Among the dedicated DSP-type instructions are:
Among the dedicated DSP-type instructions are:
16-bit data format:
- multiply (single-cycle, pipelined)
- multiply-accumulate (single-cycle, pipelined)
- complex multiply
- complex multiply-accumulate
- addsub
- fixed-point shift
32-bit data format:
- multiply
- multiply-accumutate
- multiply-subtract
The whole DSP mechanism, including parallel execution of ALU, Load/Store unit and DSP unit is fully supported by Hyperstone's DSP library hyDSP.